Field
Embodiments described herein relate to semiconductor packaging. More particularly, embodiments relate to fan out packages and methods of fabrication.
Background Information
The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. As a result, various multiple-die packaging solutions such as system in package (SiP) and package on package (PoP) have become more popular to meet the demand for higher die/component density devices. In one implementation, a memory die or package (e.g., dynamic random-access memory (DRAM)) is stacked on top of a logic die or package (e.g., application-specific integrated circuit (ASIC)) or system on chip (SoC). As the market for portable and mobile electronic devices advances larger memory capability is required of the memory die or package. In one implementation, multiple memory die are stacked vertically to increase the memory in a top memory die package. The stacked die may be interconnected using wire bonds or through silicon vias.